1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including transfer transistors that transfer a high voltage.
2. Description of the Related Art
Conventionally, as one kind of semiconductor memory devices, NAND cell type flash memories in which a plurality of memory cells capable of storing information in a nonvolatile manner are connected in series and constitute a NAND cell block have been drawing attention as they are suitable for high integration. One memory cell of a NAND cell type flash memory has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked above a semiconductor substrate via insulating films. A plurality of such memory cells are connected in series in a way that the source of one memory cell is shared as the drain of its adjoining memory cell, thereby constituting a NAND cell, which is a unit to be connected to a bit line. Such NAND cells are arranged in a matrix and constitute a memory cell array. The memory cell array is integrally formed within a p-type semiconductor substrate or a p-type well region. NAND cells aligned in the column direction of the memory cell array have their drains at one end thereof connected in common to a bit line via selector gate transistors respectively, and their sources at the other end thereof connected to common source lines likewise via selector gate transistors respectively. The control gates of the memory transistors and the gate electrodes of the selector gate transistors that are aligned along the row direction of the memory cell array are connected in common as control gate lines (word lines) or selector gate lines, respectively.
In a data writing operation, the NAND cell type flash memory transfers a voltage higher than a power supply voltage to a selected control gate line in a selected block and to non-selected control gate lines in the selected block. In order to transfer such a high voltage to the memory cells, conventional NAND cell type flash memories have a row decoder circuit including transfer transistors having a high dielectric strength (e.g., see JP2002-63795A). Peripheral circuits other than the row decoder also include many transfer transistors that transfer such a high voltage.
Flash memories have as small an area as possible not only for the cell array but also for surrounding peripheral circuits to shrink and store multivalue data (MLC: multi-level cells). Further, the row decoder can transfer a high writing potential to deal with multivalue writing.